Principal architect of VCS, the Verilog Compiled Simulator, Sanguinetti has been a major contributor to the resurgence in the use of Verilog in the design community. Born and raised in Maryland, he attended the University of Michigan, where he received his Ph.D. in Computer and Communication Sciences. After graduation, he accepted a job working for Digital Equipment Corp. (DEC) outside of Boston. He arrived at DEC in September 1977, just a few months before the company's first VAX shipped. His job was to do performance analysis, primarily on their existing PDP-11 product line.
Sanguinetti has been active in computer architecture, performance analysis, and design verification for 20 years. He is an entrepreneur, a long-time player in Silicon Valley, and someone who influenced and was influenced by the trends and characteristics unique to the EDA industry. After working for DEC, Amdahl, ELXSI, Ardent, and NeXT computer manufacturers, he founded Chronologic Simulation in 1991 and served as President until 1995. He is the principal architect of VCS, the Verilog Compiled Simulator, and has been a major contributor to the resurgence in the use of Verilog in the design community.
In May of 1998, Sanguinetti, along with Andy Goodrich and Randy Allen—who had also been at Ardent and was the author of a good part of the Ardent C Compiler—started what was called a C2 Design Automation, named CynApps. They did business as CynApps, which subsequently became Forte Design Systems. They started the company to develop a high-level design environment using C++ and to produce a synthesis product from that high-level design representation to RTL, which would then go into the standard design flow. Sanguinetti has served as Chief Technology Officer of Forte Design Systems.
He served on the Open Verilog International Board of Directors from 1992 to 1995 and has been a major contributor to the working group which drafted the specification for the IEEE 1364 Verilog standard. He has 15 publications and one patent.
